The present invention relates to a method of forming a nonvolatile memory device, and more particularly, to a method of forming a tunneling insulating layer in an electrically erasable and programmable memory device.
As is well known, in an electrically erasable and programmable read only memory (EEPROM) device, charges are injected into a floating gate and are discharged from the floating gate through a thin tunneling insulating layer so that data is programmed and erased. A significant interest in the semiconductor memory device fabrication technology field is to increase the capacity of the memory, which requires reduction in the size of a unit cell.
To reduce the size of a unit cell, the thickness of an intergate insulating layer between a floating gate and a control gate, the area of a tunneling region (a tunneling insulating layer), and/or the thickness of the tunneling insulating layer need to be reduced. When the thickness of the tunneling insulating layer is too small, the leakage current is significant. The tunneling insulating layer cannot be less than a predetermined thickness. Therefore, it is required that the area of the tunneling region be reduced.
A conventional method of forming an EEPROM device is disclosed in Japanese Patent Publication No. sho 63-246875 and in U.S. Pat. No. 5,817,557. FIGS. 1 to 4 describe such a conventional method.
First, referring to FIG. 1, an oxide layer 14 is formed on a semiconductor substrate 10 including an impurity diffusion region 12.
Next, referring to FIG. 2, after forming an interlayer insulating layer 16 on the oxide layer 14, the interlayer insulating layer 16 is patterned by a photolithography process to form an aperture 18 that limits a tunneling region. That is, after forming a photoresist layer that is a photosensitive layer on the interlayer insulating layer, the photoresist is exposed and developed by a previously prepared photo-mask to form a photoresist pattern having the aperture that limits the tunneling region. Subsequently, the interlayer insulating layer exposed by the aperture of the photoresist pattern is dry etched to form the interlayer insulating layer 16 having the aperture 18. The aperture of the photoresist pattern is directly transferred to the interlayer insulating layer. The width w1 of the aperture 18 of the interlayer insulating layer 16 is dependent on the resolution of the photolithography process.
Next, referring to FIG. 3, the oxide layer 14 exposed by the aperture 18 is wet etched to expose the impurity diffusion region 12.
Next, referring to FIG. 4, after forming a tunneling oxide film 20 on the impurity diffusion region 12 exposed by the aperture 18, polysilicon 22 for forming a floating gate is formed.
According to the conventional method of forming the EEPROM device, it is difficult to reduce the area of the tunneling region 20 due to the limitation on the resolution of the photolithography process.
Therefore, a need exists for a method of forming an EEPROM device using a photolithography process and with reduction in the area of the tunneling region.